Memory systems may encode and decode data with parity bits that provide redundancy and error correction capability for the data when read from the memory. Decoding schemes may use log likelihood ratios (LLR) associated with the bits to assist in decoding. The LLR values chosen for the bits may be based on an underlying model that assumes or estimates certain conditions related to the memory in which the bits are stored, the channel over which the bits are communicated, and the associated bit error rates. However, if the actual conditions differ from what is assumed or estimated, the LLRs that are used may not be optimal for decoding the data. In turn, the decoding process may not be as fast as it could be and/or the decoder may struggle to fully decode the data. As such, decoding schemes that utilize more optimal LLR values for decoding data may be desirable.